Illustrated portrait
MASc researcher
Deniz Sulutas
Deniz works on high-speed data conversion, where multiple converter channels must behave as one precise sampling system.
- Program
- MASc
- Supervision
- Leonard MacEachern
- Last updated
- 22 July 2026
Place in MOSAIC
The connected research tiles
Research overview
Deniz researches time-interleaved analog-to-digital converters. Time interleaving increases aggregate sampling rate by combining several converter channels and makes channel matching, sampling timing, front-end behaviour, calibration, and verification central parts of the architecture.
His work sits in MOSAIC’s long-running data-conversion program, extending a lineage in SAR conversion, capacitor arrays, calibration, timing, and low-power mixed-signal design toward higher-rate systems.
Integrated-circuit experience
Deniz completed two educational, tapeout-oriented integrated-circuit projects: a three-bit counter in the CuSOI process-design kit and an operational amplifier in GlobalFoundries 45 nm RF SOI. The projects included:
- Cadence schematic and physical design
- DRC and LVS closure
- Linux engineering environments
- Movement from functional concept to manufacturable layout
- Programming in C, C++, Java, Python, assembly, and Verilog
Broader engineering experience
Prior roles with the Office of the Auditor General and the Canadian Coast Guard exposed Deniz to requirements, documentation, usability, operational electronics, and maintainability—the practical difference between a nominally correct design and a system that others can test and trust.
Current direction
The profile will grow as the converter architecture, process context, calibration approach, and measurement plan become more specific.