Illustrated portrait
PhD researcher
Jonathan Levine
Jonathan develops high-performance FPGA accelerator architectures and tools that lower neural models toward efficient spatial hardware.
- Program
- PhD
- Supervision
- Leonard MacEachern
- Last updated
- 22 July 2026
Place in MOSAIC
The connected research tiles
Research overview
Jonathan researches high-performance FPGA accelerators for artificial intelligence. His doctoral direction connects model descriptions, quantization, architecture, compilation, and physical hardware realization.
The work includes a Python-to-RTL direction for ternary neural-network accelerators. The objective is to lower useful model structures into fully unrolled or highly spatial FPGA and ASIC logic, reducing the weight memories, DSP use, and data movement that dominate many conventional accelerators.
Research lineage
Jonathan’s earlier machine-learning accelerator work and threshold-based batch-normalization research provide the foundation for this broader direction. Threshold folding can convert batch normalization and sign activation into integer comparisons, enabling integer-only binarized-network inference.
Current methods and interests
- Quantized and ternary neural networks
- Python-to-RTL compilation
- Fully unrolled and spatial hardware architectures
- FPGA and ASIC implementation
- Integer-only inference
- Reproducible model-to-hardware verification
Selected current output
Threshold-Based Batch Normalization for Integer-Only Binarized Neural Network Inference, with Leonard MacEachern, was submitted to IEEE Embedded Systems Letters in July 2026.
Current direction
The profile will expand with compiler structure, supported network classes, architecture examples, resource and timing evidence, software artifacts, and publications as the doctoral work develops.