Adrian Sibiga
Earlier work on analog front ends for CERN-related MALTA-2 and MALTA-3 sensors. His current MASc research is in VCO-based ADCs, shown in the next stage.
Current students, supervised theses, and the training approach connecting projects across the research program.
The group spans the complete path from device behaviour to application-level interpretation. The four stages below place every current student within that end-to-end research flow. Adrian Sibiga’s work spans two stages: earlier MAPS detector front ends and current VCO-based conversion.
Electronic and photonic interfaces whose physical behaviour establishes system performance.
Earlier work on analog front ends for CERN-related MALTA-2 and MALTA-3 sensors. His current MASc research is in VCO-based ADCs, shown in the next stage.
Process-aware microring-resonator modelling with compact local neural predistortion or receiver equalization.
Circuit techniques for generating, conditioning, sampling, and converting high-speed signals.
Voltage-controlled-oscillator analog-to-digital converters (VCO ADCs), supervised solely by Leonard MacEachern.
Time-interleaved analog-to-digital converters.
Linearized active inductors for predistortion in RF, broadband, and optical interfaces.
High-speed analog-to-digital converters, with an intended time-interleaved SAR focus.
ADC sampling kickback and mitigation.
Time-to-digital converters.
Machine intelligence embodied in hardware, and AI used to create and verify that hardware.
High-performance FPGA accelerators for AI.
FPGA spiking neural networks for event-based gesture processing and SNN Hough transforms.
Efficient activation-function implementations in FPGAs.
Learning and inference applied to measured signals, modulation, and system behaviour.
AI-mediated signal modulation.
This consolidated register presents the named graduate-supervision roster, including completed, active, and discontinued programs.
The supervision record is an intellectual history of the laboratory. Semiconductor-laser models led to analog predistortion and modern photonic correction; oscillator and delay research led to synthesis, TDCs, jitter analysis, CDR, and VCO-based conversion; low-voltage ADC projects developed into calibrated, reduced-capacitor, and interleaved architectures; FPGA signal processing led into current spiking and quantized AI hardware.
Samy Ghoniemy's 2004 PhD built a physical and system model for the RF/fibre optical interface. Ayman Moktar's 2007 PhD extended the modelling to isolator-free DFB laser operation with optical feedback for analog CATV applications. Fiona Shearer's 2006 MASc implemented CMOS cubic-function circuits for third-order cancellation, while Zhan Xu's 2010 PhD developed adaptive second- and third-order correction for directly modulated lasers. Together they establish a durable model-and-correct lineage.
Karim Abdelhalim's subthreshold biomedical ADCs reported 8.09 and 10.3 pJ per conversion cycle. Lado Filipovic's low-power 10-bit ADC and Octavian Stelescu's femtojoule comparator-assisted binary-search ADC extended that converter lineage. Niranjan Iyer's Vernier time-difference amplifier and Tianshuo Zhao's MCML time-to-digital converter carried the work into precision timing. Later theses developed continuous DAC-mismatch correction, reduced-capacitor SAR arrays, and algorithm-generated SAR switching sequences.
Daniel Lanfranconi's 2014 MASc developed a reduced-capacitor eight-bit SAR ADC. Octavian Stelescu's 2012 MASc developed a femtojoule-per-conversion comparator-assisted binary-search (CAB) ADC. David Berton's 2018 MASc used a backtracking algorithm to generate a 10-bit SAR switching sequence with only 25 unit capacitors. Seth Thompson's 2025 MASc combines a non-standard capacitor array, clock boosting, and a voltage-controlled delay element; schematic studies report approximately 9.5–9.7 effective bits after compensation at 10 kS/s, 1.82 μW, and 226.5 fJ per conversion step.
Ruihang Wang's 2025 MASc develops a fabricated mixed-signal SNN for Hough-transform line detection, reporting 266.1 pJ per frame in 3 mm². Jonathan Levine's 2025 MASc compiles binarized networks to bespoke FPGA hardware, with reported MNIST latencies near 85 ns and a jet-tagging example near 23 ns. These results are thesis-specific and do not imply identical performance in later systems.
This catalogue presents the graduate theses listed in the supervision record. Repository links are provided where available; entries without links retain the confirmed student, degree, year, and thesis title.
| Year | Student and thesis | Degree | Record |
|---|---|---|---|
| 2026 | Liam McPherson Sensor Based Activity Classification and Functional Capacity Assessment After Total Hip Arthroplasty | MASc (Mechanical Engineering) | Defended September 17, 2026 |
| 2025 | Seth Thompson Interleaved SAR-ADC with Reduced Capacitors | MASc | Under embargo |
| 2025 | Ruihang Wang Application-Specific Integrated Circuit Spiking Neural Network for Parallel Hough Transform | MASc | Under embargo |
| 2025 | Jonathan Aaron Levine Hardware-Accelerated Binarized Neural Networks | MASc | Under embargo |
| 2019 | Colin Fernandes Electrospun PEDOT:PSS Electrolytic Capacitor Electrodes for Microelectronic Energy Storage | MASc | Record ↗ |
| 2018 | Ghazaleh Vazhbakht Configurable FPGA-Based Outlier Detection for Time Series Data | MASc | Record ↗ |
| 2018 | David Berton Backtracking Algorithm-Aided Design of a 10-Bit SAR ADC | MASc | Record ↗ |
| 2017 | Xinjie Wang Reduction of Power Supply Induced Jitter with Applications to DDR Controllers | PhD | Record ↗ |
| 2017 | Tianshuo Zhao A High Resolution of MCML-Based Time-to-Digital Converter Implementation | MASc | Record ↗ |
| 2017 | Satyanarayana Shashank Brahmandlapalli Determination of Bioimpedance Using Multi-Frequency Bio-electrical Impedance Analysis | MASc | Record ↗ |
| 2016 | Ruixue Wang A Low Power 8 to 1 Analog Multiplexer for Bio-Signal Acquisition System with a Function of Amplification | MASc | Record ↗ |
| 2014 | Niranjan Iyer Linearity Improvement in Vernier Delay Chain Based Time Difference Amplifiers | MASc | Record ↗ |
| 2014 | Nick Stupich Low Power Parallel Rolling Shutter Artifact Removal | MASc | Record ↗ |
| 2014 | Daniel Lanfranconi Reduced Capacitor Eight Bit SAR ADC | MASc | Record ↗ |
| 2012 | Ziad El-Khatib Highly-linearized CMOS distributed bidirectional amplifier with cross-coupled compensator for wireless communications | PhD | Record ↗ |
| 2012 | Octavian Stelescu Femto Joule per conversion 8-bit comparator assisted binary search ADC | MASc | Record ↗ |
| 2010 | Zhan Xu A predistortion circuit for direct modulated lasers for radio over fiber applications | PhD | Record ↗ |
| 2009 | Lado Filipovic Low power 10-bit ADC | MASc | Record ↗ |
| 2009 | Ghyslain Gagnon Continuous compensation of binary-weighted DAC nonlinearities in bandpass delta-sigma modulators | PhD | Record ↗ |
| 2008 | Sinisa Milicevic A frequency synthesizer with frequency divider and frequency multiplier for spur reduction | PhD | Record ↗ |
| 2007 | Karim Abdelhalim Ultra low power ADC for biomedical applications | MASc | Record ↗ |
| 2007 | Ayman Moktar Isolator-free DFB laser for analog CATV applications | PhD | Record ↗ |
| 2006 | Ziad El-Khatib Fully-integrated fully-differential silicon RF CMOS distributed amplifier based on multi-Tanh linearization principle | MASc | Record ↗ |
| 2006 | Fiona Shearer CMOS analog cubing circuits for radio-over-fiber predistortion | MASc | Record ↗ |
| 2006 | Daniel Olszewski Tunable filter and receive signal strength indicator for detecting whitespace in the frequency spectrum | MASc | Record ↗ |
| 2006 | Celine Fletcher VCO phase noise reduction technique | MASc | Record ↗ |
| 2005 | Yasser Soliman CMOS LNA for impulse-radio UWB | MASc | Record ↗ |
| 2005 | Sinisa Milicevic A multi-band voltage-controlled ring oscillator | MASc | Record ↗ |
| 2005 | Mark Houlgate Adaptable MOS current mode logic for multi-band frequency synthesizers | MASc | Record ↗ |
| 2004 | Samy Ghoniemy RF/fiber optical interface for microcellular wireless transceivers | PhD | Record ↗ |
Students work across levels of abstraction: physical plant and measurement, device and circuit models, schematic and layout, digital support logic, FPGA or ASIC mapping, software tooling, and the evidence needed to decide whether a result is valid.