Subthreshold biomedical conversion
Karim Abdelhalim developed two eight-bit ADCs operating down to 0.3 V in 0.13 μm CMOS. Measured energy was 10.3 and 8.09 pJ per conversion cycle; one architecture achieved 7.54 effective bits and 62.2 dB SFDR.
Analog Circuits and Data Conversion
A continuous program in analog blocks, conversion, calibration, sampling, timing, and adaptive front ends.
A continuous converter program
The ADC program runs from subthreshold biomedical conversion through calibrated capacitor arrays, reduced-capacitor and binary-search SAR architectures, continuous DAC correction, timing conversion, sampling physics, and contemporary interleaved and VCO-based conversion. The common theme is not one topology: it is how architecture, calibration, device behaviour, and implementation parasitics determine useful precision.
Analog infrastructure around the converter
Converters depend on comparators, references, bias networks, amplifiers, multiplexers, samplers, delay elements, clocks, layout, extraction, and test. Biomedical acquisition theses added low-noise routing and amplification; TDC and jitter work treated time as an analog quantity; current sampling-kickback work returns to the interaction between front-end devices and converter decisions.
Selected evidence
Continuous DAC-mismatch correction
Ghyslain Gagnon calibrated binary-weighted multibit DAC elements while the delta-sigma loop remained closed. A fabricated modulator improved measured SNR from 57.3 to 64.5 dB while the storage requirement grew linearly with quantizer resolution.
Algorithm-generated SAR architecture
David Berton used backtracking to generate the switching sequence for a 10-bit SAR ADC using 25 unit capacitors rather than a conventional 1024-unit binary array. The reported design achieved 9.39 effective bits, 1.65 μW at 10 kS/s, and 246 fJ per conversion step.
Interleaved reduced-capacitor SAR ADC
Seth Thompson combined a non-standard capacitor array, clock boosting, and a voltage-controlled delay element. Schematic results report approximately 9.5–9.7 effective bits after compensation, 1.82 μW, and 226.5 fJ per conversion step at 10 kS/s; layout dimensions are approximately 195 × 214 μm.
SAR, interleaving, and sampling
Current higher-rate directions examine the cost of time interleaving: channel offset and gain mismatch, clock skew, front-end bandwidth, kickback, calibration overhead, and layout asymmetry. Reduced-capacitor switching remains valuable when energy and area matter, but only when parasitics and calibration preserve the intended transfer characteristic.
VCO conversion and operational validity
VCO-based conversion links oscillator phase, quantization, calibration profiles, and operating-point drift. A current research question is operational rather than purely numerical: after bias, temperature, capacitance, memory path, or implementation changes, what inexpensive observation is sufficient to decide whether an existing profile can still be trusted or recalibration is required?