Neuromorphic, spiking, binarized, ternary, and quantized computation on FPGA and ASIC platforms.
AI hardware is useful only when the representation, architecture, and implementation match the observable task. This program studies event-driven computation, severe quantization, compiler-generated RTL, and fixed-point nonlinear blocks while keeping latency, state, memory traffic, resource use, power evidence, and accuracy in the same account.
Gesture, line, and Hough-transform applications replace dense frame-by-frame arithmetic with spike events, local state, and parallel accumulation. The published FPGA work demonstrates efficient kernels; the mixed-signal thesis line investigates what happens when part of the computation is realized in analog neuromorphic circuits.
Binarized and ternary networks trade arithmetic precision for explicit thresholds, bitwise operations, and compact state. Compiler-driven flows connect a trained model to generated RTL, analytic resource estimates, testbenches, synthesis, and measured or mapped evidence rather than stopping at software accuracy.
The published Early Access article implements a kernel-transformed spiking Hough architecture on a Zynq UltraScale+ FPGA. IEEE reports 13 μs processing for 100 × 100 images using 6.7 KiB of state, with hardware utilization independent of image size up to the configured maximum.
A low-cost FPGA SNN applies event-driven computation to gesture data, testing how much recognition capability can be retained under constrained memory, latency, and energy budgets.
Ruihang Wang developed an analog mixed-signal SNN for parallel Hough voting in 0.18 μm CMOS. The thesis reports 266.1 pJ per frame in 3 mm², with 72% measured classification accuracy and 93% measured detection for the tested system.
Jonathan Levine used an Etcher/tinygrad flow to create bespoke FPGA BNN accelerators and an analytical LUT model. Reported MNIST designs reached 93.13–96.15% accuracy at approximately 85 ns; a jet-tagging example reached 67.45% at roughly 23 ns using 1,362 LUTs.
Ghazaleh Vazhbakht mapped configurable ARMA modelling and anomaly detection to an FPGA, reporting 99% detection accuracy, 1.05% type-I error, 35 million points per second, and 1.14 W in the studied configuration.
Current work on replicated GELU banks and related nonlinear blocks evaluates word length and lookup-table size through the downstream system output. The design objective is therefore not simply the local error of one function evaluation, but the precision and hardware cost needed to protect the quantity the enclosing computation actually uses.