Frequency synthesis and spur control
Sinisa Milicevic combined multiplication and division in a programmable synthesizer feedback path to reduce reference-related spurs, targeting a 10 GHz output from a 20 MHz reference with 500 kHz channel spacing.
Theoretical Foundations
Quantization, synchronization, clocks, spectra, graphs, and application-level performance limits.
Why theory appears in a circuit program
The theoretical branch asks which structure actually controls an engineering outcome. Quantization, timing, spectral content, local inconsistency, and model reduction become useful when they predict a limit, identify a failure, or show where a correction should be placed in a realized system.
Quantization under real timing
Classical Bennett-style reasoning is a starting point for asking what changes when converter decisions occur at multiple times, when clocks are correlated, or when settling and internal timing are part of the quantizer. The objective is a limit that corresponds to the implemented decision process rather than an idealized scalar quantizer.
Synchronization and clock translocation
A clock is treated as a coordinate system that makes another signal interpretable. Oscillators, PLLs, MDLLs, TDCs, CDR, retiming, deskew, VCO conversion, and asynchronous sensor readout are therefore related problems: they move, reconstruct, compare, or measure timing information across devices and domains.
Spectra, graphs, and observables
Spectral structure can expose jitter, nonlinear products, resonant dynamics, periodic error, and channel loss that a final scalar metric hides. Graph-based consistency asks whether local pairwise timing or calibration constraints admit a coherent global state and whether the irreducible cycle residual can guide correction or relaxation.
Selected supervised foundations
Jitter, power integrity, and timing models
Xinjie Wang's dissertation connects MDLL reference-spur reduction, a compact power-supply-induced-jitter transfer function for CMOS buffer chains, broadband on-die power-grid equivalent circuits, and a DDR-controller clock-distribution case study.
Time-to-digital conversion
Tianshuo Zhao implemented an MCML time-to-digital converter in 0.13 μm CMOS with configurable reported resolutions of approximately 8.24, 10.83, 12.98, and 14.3 ps over a nine-bit range.
Application-optimal limits
The research uses the downstream observable to decide what approximation is sufficient. A local waveform match is not enough if the link eye, converter profile, detector hit survival, neural output, or protected system quantity changes. This observable-space discipline connects the theoretical branch to surrogate models, calibration, and output-aware hardware.